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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">TRCIDR3, ID Register 3</h1><p>The TRCIDR3 characteristics are:</p><h2>Purpose</h2>
        <p>Returns the base architecture of the trace unit.</p>
      <h2>Configuration</h2><p>External register TRCIDR3 bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-trcidr3.html">TRCIDR3[31:0]</a>.</p><p>This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCIDR3 are <span class="arm-defined-word">RES0</span>.</p><h2>Attributes</h2>
        <p>TRCIDR3 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_31">NOOVERFLOW</a></td><td class="lr" colspan="3"><a href="#fieldset_0-30_28">NUMPROC[2:0]</a></td><td class="lr" colspan="1"><a href="#fieldset_0-27_27">SYSSTALL</a></td><td class="lr" colspan="1"><a href="#fieldset_0-26_26">STALLCTL</a></td><td class="lr" colspan="1"><a href="#fieldset_0-25_25">SYNCPR</a></td><td class="lr" colspan="1"><a href="#fieldset_0-24_24">TRCERR</a></td><td class="lr" colspan="1"><a href="#fieldset_0-23_23">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-22_22">EXLEVEL_NS_EL2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-21_21">EXLEVEL_NS_EL1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-20_20">EXLEVEL_NS_EL0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-19_19">EXLEVEL_S_EL3</a></td><td class="lr" colspan="1"><a href="#fieldset_0-18_18">EXLEVEL_S_EL2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-17_17">EXLEVEL_S_EL1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-16_16">EXLEVEL_S_EL0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-15_14">RES0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-13_12">NUMPROC[4:3]</a></td><td class="lr" colspan="12"><a href="#fieldset_0-11_0">CCITMIN</a></td></tr></tbody></table><h4 id="fieldset_0-31_31">NOOVERFLOW, bit [31]</h4><div class="field">
      <p>Indicates if overflow prevention is implemented.</p>
    <table class="valuetable"><tr><th>NOOVERFLOW</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Overflow prevention is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Overflow prevention is implemented.</p>
        </td></tr></table>
      <p>If TRCIDR3.STALLCTL == 0 then this field is 0.</p>
    </div><h4 id="fieldset_0-30_28">NUMPROC, bits [13:12, 30:28]</h4><div class="field">
      <p>Indicates the number of PEs available for tracing.</p>
    <table class="valuetable"><tr><th>NUMPROC</th><th>Meaning</th></tr><tr><td class="bitfield">0b00000</td><td>
          <p>The trace unit can trace one PE.</p>
        </td></tr></table><p>This field reads as <span class="binarynumber">0b00000</span>.</p>
<p>The NUMPROC field is split as follows:</p>
<ul>
<li>NUMPROC[2:0] is TRCIDR3[30:28].
</li><li>NUMPROC[4:3] is TRCIDR3[13:12].
</li></ul></div><h4 id="fieldset_0-27_27">SYSSTALL, bit [27]</h4><div class="field">
      <p>Indicates if stalling of the PE is permitted.</p>
    <table class="valuetable"><tr><th>SYSSTALL</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Stalling of the PE is not permitted.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Stalling of the PE is permitted.</p>
        </td></tr></table><p>The value of this field might be dynamic and change based on system conditions.</p>
<p>If TRCIDR3.STALLCTL == 0 then this field is 0.</p></div><h4 id="fieldset_0-26_26">STALLCTL, bit [26]</h4><div class="field">
      <p>Indicates if trace unit implements stalling of the PE.</p>
    <table class="valuetable"><tr><th>STALLCTL</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Stalling of the PE is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Stalling of the PE is implemented.</p>
        </td></tr></table></div><h4 id="fieldset_0-25_25">SYNCPR, bit [25]</h4><div class="field">
      <p>Indicates if an implementation has a fixed synchronization period.</p>
    <table class="valuetable"><tr><th>SYNCPR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="ext-trcsyncpr.html">TRCSYNCPR</a> is read/write so software can change the synchronization period.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="ext-trcsyncpr.html">TRCSYNCPR</a> is read-only so the synchronization period is fixed.</p>
        </td></tr></table>
      <p>This field reads as 0.</p>
    </div><h4 id="fieldset_0-24_24">TRCERR, bit [24]</h4><div class="field">
      <p>Indicates forced tracing of System Error exceptions is implemented.</p>
    <table class="valuetable"><tr><th>TRCERR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Forced tracing of System Error exceptions is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Forced tracing of System Error exceptions is implemented.</p>
        </td></tr></table>
      <p>This field reads as 1.</p>
    </div><h4 id="fieldset_0-23_23">Bit [23]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-22_22">EXLEVEL_NS_EL2, bit [22]</h4><div class="field">
      <p>Indicates if Non-secure EL2 is implemented.</p>
    <table class="valuetable"><tr><th>EXLEVEL_NS_EL2</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Non-secure EL2 is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Non-secure EL2 is implemented.</p>
        </td></tr></table></div><h4 id="fieldset_0-21_21">EXLEVEL_NS_EL1, bit [21]</h4><div class="field">
      <p>Indicates if Non-secure EL1 is implemented.</p>
    <table class="valuetable"><tr><th>EXLEVEL_NS_EL1</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Non-secure EL1 is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Non-secure EL1 is implemented.</p>
        </td></tr></table></div><h4 id="fieldset_0-20_20">EXLEVEL_NS_EL0, bit [20]</h4><div class="field">
      <p>Indicates if Non-secure EL0 is implemented.</p>
    <table class="valuetable"><tr><th>EXLEVEL_NS_EL0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Non-secure EL0 is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Non-secure EL0 is implemented.</p>
        </td></tr></table></div><h4 id="fieldset_0-19_19">EXLEVEL_S_EL3, bit [19]</h4><div class="field">
      <p>Indicates if EL3 is implemented.</p>
    <table class="valuetable"><tr><th>EXLEVEL_S_EL3</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>EL3 is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>EL3 is implemented.</p>
        </td></tr></table></div><h4 id="fieldset_0-18_18">EXLEVEL_S_EL2, bit [18]</h4><div class="field">
      <p>Indicates if Secure EL2 is implemented.</p>
    <table class="valuetable"><tr><th>EXLEVEL_S_EL2</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Secure EL2 is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Secure EL2 is implemented.</p>
        </td></tr></table></div><h4 id="fieldset_0-17_17">EXLEVEL_S_EL1, bit [17]</h4><div class="field">
      <p>Indicates if Secure EL1 is implemented.</p>
    <table class="valuetable"><tr><th>EXLEVEL_S_EL1</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Secure EL1 is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Secure EL1 is implemented.</p>
        </td></tr></table></div><h4 id="fieldset_0-16_16">EXLEVEL_S_EL0, bit [16]</h4><div class="field">
      <p>Indicates if Secure EL0 is implemented.</p>
    <table class="valuetable"><tr><th>EXLEVEL_S_EL0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Secure EL0 is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Secure EL0 is implemented.</p>
        </td></tr></table></div><h4 id="fieldset_0-15_14">Bits [15:14]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-11_0">CCITMIN, bits [11:0]</h4><div class="field"><p>Indicates the minimum value that can be programmed in <a href="ext-trcccctlr.html">TRCCCCTLR</a>.THRESHOLD.</p>
<p>If <a href="ext-trcidr0.html">TRCIDR0</a>.TRCCCI == 1 then the minimum value of this field is <span class="hexnumber">0x001</span>.</p>
<p>If <a href="ext-trcidr0.html">TRCIDR0</a>.TRCCCI == 0 then this field is zero.</p></div><h2>Accessing TRCIDR3</h2><h4>TRCIDR3 can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>ETE</td><td><span class="hexnumber">0x1EC</span></td><td>TRCIDR3</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When OSLockStatus() or !IsTraceCorePowered(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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